74HC73

74HC73

Non-returnable
Dual JK flip-flop with reset; negative-edge trigger
The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC
standard no. 7A.
The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (n R) is an asynchronous active LOW input. When LOW, it overrides the clock
and data inputs, forcing the nQ output LOW and the nQ output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
₹30.00

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